1. Field of the Invention
The present invention relates to interrupts within a computer system, and more specifically to an interrupt controller for more efficient handling of interrupts in a computer system.
2. Description of the Related Art
A typical computer system contains at least one interrupt service provider, usually a central processing unit (CPU), and a number of input/output (I/O) devices peripheral to the CPU(s). These I/O devices commonly include hard disk drives, floppy disk drives, video adapters, parallel ports, serial ports, and other similar I/O type devices. An I/O device may need to alert the CPU(s) or request service when it completes a task or has a status change, such as finishing a data transfer, completing an operation, receiving data, or the occurrence of an error condition.
The typical mechanism for an I/O device to request service from the CPU(s) involves an interrupt request. An interrupt request is generally a hardware signal sent from the requesting device to a CPU notifying the CPU that the I/O device requires service. Other system devices such as timers, direct memory access (DMA) controllers, and other processors may generate interrupt request signals.
One advantage of using interrupts over other techniques, such as polling, is that the CPU is free to perform other operations between interrupts. When a CPU receives an interrupt request, it stops executing the current instruction routine, saves its state, and jumps to an interrupt service routine. The interrupt service routine includes instructions specific to the device requesting the interrupt so that the CPU can respond to the device condition or status change that instigated the interrupt request. When the interrupt service routine is completed, the CPU restores its state and returns to its location prior to the interrupt.
Referring to FIG. 1, a computer system 100 using interrupts is shown according to the prior art. The computer system 100 includes a CPU 110, and a main memory system 120 coupled to a host bus 180. The main memory system 120 typically includes a memory controller and system memory (not shown). A bus bridge 140 is coupled to the host bus 180 and an expansion bus 190 and typically includes a DMA controller (not shown). The expansion bus 190 typically conforms to a popular bus standard such as the Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Microchannel Architecture (MCA), or Peripheral Component Interconnect (PCI). Alternatively, multiple expansion busses are included, such as a PCI bus further coupled to an ISA bus. Several I/O devices 150, 160, 170 are coupled to the expansion bus 190. The I/O devices 150, 160, 170 are typically devices such as a floppy disk drive, video adapter, parallel port, or other devices as are well known in the art.
The bus bridge 140 and the I/O devices 150, 160, 170 generate interrupt requests along interrupt request lines 142, 152, 162, 172, respectively, to notify the CPU 110 that service is needed. The interrupt, requests along lines 142, 152, 162, 172 are collected by a programmable interrupt controller (PIC) 130. The programmable interrupt controller 130 is coupled to the host bus 180 and the expansion bus 190. Generally, when the programmable interrupt controller 130 receives one of the interrupt requests along lines 142, 152, 162, 172 it sends an interrupt signal on line 132 to the CPU 110. When the CPU 110 receives the interrupt signal on line 132, it finishes its current operation and sends an interrupt acknowledge along line 112 to the programmable interrupt controller 130. When the programmable interrupt controller 130 receives the interrupt acknowledge it sends an interrupt vector to the CPU 110 over the host bus 180. The interrupt vector indicates the location of the appropriate interrupt service routine to the CPU 110.
Generally speaking, in a typical system, a programmable interrupt controller receives the interrupt request signals from the various system devices and organizes the requests to be sent to the CPU(s). Normally, the programmable interrupt controller includes a mask register associated with each interrupt. The mask register is programmed to block a certain interrupt so that the CPU will not be interrupted by that particular interrupt. The programmable interrupt controller contains other registers associated with each interrupt for indicating information such as the interrupt status and interrupt vector for each interrupt.
The programmable interrupt controller also functions as an overall manager for interrupt requests. It receives the interrupt requests from each device, determines which requests are sent to the CPU(s) first, and handles new incoming interrupt requests. Some devices have more immediate need for service than other devices. Therefore, the programmable interrupt controller provides a priority system to be assigned to the interrupt requests. Generally, the programmable interrupt controller determines which one of the current interrupt requests has the highest priority and forwards that request to a CPU first. Occasionally, an interrupt request will be received by the programmable interrupt controller that has a higher priority than the interrupt request currently being serviced. One technique commonly employed to deal with this situation is interrupt nesting. In interrupt nesting, the programmable interrupt controller allows the incoming interrupt request to interrupt the servicing of an earlier interrupt request currently being serviced if the incoming interrupt request is of higher priority than the earlier interrupt request currently being serviced. If the incoming interrupt request is not of higher priority, it is put in order with other pending interrupt requests, usually according to the source of the interrupt. However, this requires that the queue in each nesting buffer be of sufficient size to accommodate all of the potential interrupt sources. Accordingly, there is a need for an interrupt controller that will optimize the storage of pending interrupts.
In addition to resolving priority among devices needing to be serviced, the controller will also need to resolve a task priority to determine to which CPU in a multiple CPU system the interrupt should be sent. Typically, the CPU or device servicing an interrupt is assigned a task priority according to the level of importance of the task being performed. When a new task is to be performed, it is customary to search for a device that has the lowest task priority, and assign the new task to that device (for an interrupt that does not have a destination previously specified). However, if more than one device shares the same task priority, there is a chance that one device will always end up performing the new task, while other devices at the same task priority level may never be assigned the task. Therefore, it would be desirable to introduce a scheme to ensure that no such uneven distribution of system load occurs.
It can easily be understood that a relatively large amount of time may pass before an interrupt request is serviced, especially if the interrupt request has a low priority. The amount of time between the assertion of an interrupt request and the actual servicing of the interrupt request is called the interrupt latency. A problem associated with large interrupt latencies is that the status of the requesting device may change during the latency period so that servicing is no longer required, and thus the CPU will unnecessarily execute the interrupt service routine. This unnecessary execution of interrupt service routines results in extra overhead because the CPU spends time trying to service a condition which no longer exists, and thus overall system throughput is degraded. Therefore, a technique is desired for preventing invalid interrupt requests from being sent to the CPU.
A typical programmable interrupt controller implementation includes storage registers associated with each interrupt which store the current state of the interrupt, such as pending or in-service. Also, storage registers are required to store information for each interrupt request, such as the vector information and the priority level. Interrupt request receiving circuitry in the programmable interrupt controller coordinates the interrupt request state and other information with processor interface circuitry in the programmable interrupt controller. For systems with a large number of interrupt request sources, the amount of circuitry required to implement the above storage registers is very large. If the system supports multiple CPUs, then the above storage registers may need to be repeated in the programmable interrupt controller for each CPU, further increasing the size of the circuitry. Also, a large amount of circuitry is required to coordinate, manage, and access the storage registers. For an integrated programmable interrupt controller, a large portion of the chip area is require to implement the storage registers and associated circuitry. Therefore, it is desirable to have a more efficient way of referencing and implementing the required storage information for each interrupt.
Additionally, a typical programmable interrupt controller includes control circuitry associated with each interrupt request input to track the changes in the state of the interrupt request. This control circuitry includes some storage elements that are used to store the current state, and some combinatorial logic to determine the outputs and the next state based on the current state and other inputs. Similar control circuitry is required for each interrupt request input. If the number of interrupt request inputs is large, the amount of circuitry required to implement all the control circuitry can become prohibitively large. Therefore, a more efficient way of implementing the interrupt request control circuitry is desired.
In addition, a centralized programmable interrupt controller in a multiprocessing environment must be able to transmit a variety of interrupts, typically sending each to a different pin on a processor. For example, a 486-type processor has pins for system management interrupts (SMI), non-maskable interrupts (NMI), RESET interrupts, and maskable interrupts. In addition, there may be other functions, such as processor initialization and interrupt acknowledge that must be performed on a per processor basis and thus require their own pin. One way for a programmable interrupt controller to support multiple processors is for the programmable interrupt controller to have a pin for every interrupt in every processor. In a large multiprocessing system, the number of pins required can become prohibitive. As such, there is a need for a way to reduce the number of pins required on a programmable interrupt controller to support a large number of interrupts in a multi-processing environment.